1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and particularly relates to a semiconductor integrated circuit which includes a clock supply system to reduce clock skew when multiple power supplies are used inside.
2. Related Background Art
Hitherto, the power supply voltages of sequential circuits and combinational circuits in one semiconductor chip have a fixed value. In some cases, however, to reduce power consumption, the power supply voltage of some block (hereinafter referred to as a core) is decreased. Moreover, the power supply voltage of the core may be changed depending on applications executed by this core. When the power supply voltage of the core is changed, the propagation delay of a clock supplied to the core is also changed, which leads to an increase in the clock skew of the entire one semiconductor chip.
FIG. 1 is a block diagram showing the connection relationship of a related semiconductor integrated circuit in a semiconductor chip. In the example in FIG. 1, the semiconductor integrated circuit includes a clock generating circuit 1, a core A, and a core B. The clock generating circuit 1 generates a clock signal and supplies the clock signal to the core A and the core B.
The core A and the core B are constituted by sequential circuits and combinational circuits, and it is assumed that data is delivered between the core A and the core B. Namely, the core means a constitutional unit to realize a predetermined function.
FIG. 2 is a block diagram showing the internal configuration of the clock generating circuit 1, FIG. 3 is a block diagram showing a clock supply system inside the core A, and FIG. 4 is a block diagram showing a clock supply system inside the core B.
An oscillation clock signal is outputted from a PLL circuit 10 included in the clock generating signal 1 in FIG. 2, and this clock signal is supplied to flip-flop circuits A11 and A12 of the core A through buffers A1 to A5 and supplied to flip-flop circuits B11 and B12 of the core B through buffers C1 and B1 to B5.
As can be seen from FIG. 1 to FIG. 4, hitherto, the power supply voltage is fixed in the semiconductor chip, and hence, propagation delays of the clock signal from the PLL circuit 10 to the flip-flop circuits A11, A12, B11, and B12 which are sequential circuits are also fixed. In other words, since delay values of the buffers A1 to A5 and B1 to B5 which are delay elements included in a clock system are fixed, a reduction in clock skew is realized by designing a clock signal supply system with consideration given to the propagation delays of the clock signal from the PLL circuit 10 to the flip-flop circuits A11, A12, B11 and B12 which are the sequential circuits.
When the power supply voltage of the core A is made variable, however, the delay values of the buffers A1 to A5 change, and accordingly the propagation delays of the clock signal to the flip-flop circuits A11 and A12 which are the sequential circuits change. This causes a problem that the propagation delays of the clock signal to the flip-flop circuits A11 and A12 and the propagation delays of the clock signal to the flip-flop circuits B11 and B12 cannot match.